Digital Logic & Computer Architecture Basics

This is the layer under the layer: before there's a processor to run C on, there's a handful of logic gates wired together, and everything above is built out of more of the same idea, repeated at scale.

Logic gates are the alphabet. AND outputs 1 only if both inputs are 1; OR outputs 1 if either is; NOT inverts a single input; XOR outputs 1 only if its inputs differ. NAND (AND then NOT) and NOR are "universal" gates -- either one alone can be wired together to build every other gate, which is a fact interviewers like precisely because it's surprising the first time you hear it.

Combinational logic has no memory: same inputs, same outputs, instantly (in principle -- real gates have propagation delay). An adder built from gates is combinational: feed it two numbers, it outputs their sum, and it forgets the moment the inputs change. Sequential logic has memory, built from a flip-flop -- the simplest circuit that can hold one bit and change it only when a clock edge tells it to. Chain enough flip-flops together and you have a register: a small, fast storage location the processor can read and write in a single cycle, which is the whole reason registers are faster than RAM -- there's no bus, no address decode, just wires directly into the ALU.

The ALU (Arithmetic Logic Unit) is the part that actually computes -- addition, subtraction, the bitwise operations from the previous topic, comparisons -- and a control unit feeds it operands from registers and routes its result back. That register-ALU-register loop, repeated once per instruction, is the machine underneath every line of C you write.

Von Neumann vs. Harvard architecture is about whether instructions and data share one memory or two. A von Neumann machine stores code and data in the same memory space, fetched over the same bus -- simple, flexible, and it means a buggy write can (in principle) corrupt executable code, which is part of why stack-overflow-style attacks are possible at all. A Harvard architecture keeps instruction memory and data memory physically separate with separate buses -- common in microcontrollers, where it lets an instruction fetch and a data access happen in the same cycle instead of contending for one bus, and where it's an actual security property: you cannot overwrite code by overflowing a data buffer.